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? semiconductor components industries, llc, 2017 january, 2018 ? rev.1 1 publication order number: FUSB303/d FUSB303 FUSB303 autonomous usb type-c port controller with i 2 c and gpio control description the FUSB303 device is a fully autonomous usb t ype?c ? controller optimized for 15 w or less applications. the FUSB303 offers cc logic detection for source port role, sink port role, drp, and accessory detection support, as well as dead battery support as defined in usb?c specifications. the FUSB303 features configurable address i 2 c access to support multiple ports per system or it can operate autonomously configured by just pins. the FUSB303 features ultra?low power during operation, and an ultra?thin, 12?lead qfn package. features ? fully autonomous usb?c ? port controller ? supports latest t ype?c ? specification release 1.3 ? source, sink, and drp port role configuration with optional accessory support ? try.src and try.snk modes for preferring source role or sink role respectively ? v dd operating range, 2.85 v ? 5.5 v ? typical low power operation: i cc < 10 a ? gpio and i 2 c configuration ? max 28 v dc tolerance on id, vbus_det, cc1 and cc2 ? dead battery support (sink port role when no power applied) ? 4 kv hbm esd protection for connector pins ? small packaging, 12 lead qfn (1.6 mm 1.6 mm 0.375 mm) applications ? smartphones ? tablets ? laptops ? accessoires ? industrial ? power banks www. onsemi.com qfn12 case 722ag marking diagram xxxx = specific device code f = wafer fab a = assembly site wl = lot id yy = year ww = work week = pb-free package 1 xxxx fawlyy - ww (note: microdot may be in either location) see detailed ordering and shipping information on page 3 o f this data sheet. ordering information
FUSB303 www. onsemi.com 2 figure 1. typical i 2 c application vbus int_n sda scl src, src+acc, snk, snk+acc, drp & drp+acc state machines cc1 cc2 gnd FUSB303 i2c slave osc bg usb type? c connector io buffers & controller 1.8v vddio int_n / out3 sda / out1 scl / out2 en_n addr/ orient 900k port/ debug_n vdd id vbus_det (debug boot signals) system test vbus sys fan 54511 3.2a charger bat pmid sw boot 4. 7 f cc switches, i(rp)/rd & comparators block vdd processor (i2c master section) id fusb340 (usb 3.1 2:1 mux) gnd usb type? c connector ss tx1/rx1 ss tx2/rx2 ss tx/rx io buffers & controller usb 2.0 &3.1 phy int_n / out3 sda / out1 scl / out2 port/ debug_n en_n addr/ orient s internal pull? up internal pull? up gpio[1] gpio[2] snk or src gpio[1:2]=10/11: default gpio[1:2]=01: 1.5a gpio[1:2]=00: 3a (debug boot signals) system test vbus src, src+acc, snk, snk+acc, drp & drp+acc state machines cc1 cc2 FUSB303 i2c slave osc bg cc switches, i(rp)/rd & comparators block vbus_det vdd id vbus sys fan54511 3.2a charger bat pmid sw boot gpio[3] vdd processor (usb2.0/3.1 phy section) internal pull? up gpio[4] if no processor available, tie id to gate of source pmosfet, en_n to gnd and leave sda/out1 & scl/out2 unconnected. figure 2. typical gpio application
FUSB303 www. onsemi.com 3 ordering information table table 1. available part numbers part number top mark operating temperature range package packing method ? FUSB303tmx ud ?40 to 85 c 12?lead ultra?thin molded leadless package (qfn) 1.6 mm x 1.6 mm x 0.375 mm tape and reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. block diagram figure 3. FUSB303 block diagram src, src+acc, snk, snk+acc, drp & drp+acc state machines vdd int_n / out3 sda / out1 scl / out2 cc1 cc2 gnd vbus_det fusb 303 port / debug _n id i2c slave cc switches , i(rp)/rd & comparators block osc en _n bg addr/ orient io buffers & controller vdd
FUSB303 www. onsemi.com 4 pin configuration figure 4. FUSB303 pin assignment (top through and bottom views) int_n/ out3 sda / out1 scl / out2 port/ debug_n cc1 en_n cc2 id addr/ orient gnd vdd vbus_det 2 12 11 10 9 8 7 6 5 4 3 id sda / out1 scl / out2 vdd cc2 vbus_det cc1 int_n / out3 gnd addr/ orient port/ debug_n en_n 1 2 3456 7 8 9 10 11 12 1 pin 1 to p through view bottom layout view pin 1
FUSB303 www. onsemi.com 5 pin descriptions table 2. pin descriptions pin # name type description usb type?c connector interface 1, 2 cc1, cc2 i/o type?c configuration channel pins used for usb?c receptacles 4 vbus_det input vbus input pin for attach and detach detection power and ground 10 gnd ground ground 12 vdd power input supply voltage i 2 c signal interface 6 int_n/out3 open?drain output int_n/out3 is a dual function pin. when in i 2 c mode (see addr/orient pin), it is the active low open drain interrupt output used to prompt the processor to read the i 2 c register bits. when the device is in gpio mode (see addr/orient pin), this pin is out3, an open drain output low = audio accessory detected high?z = audio accessory not detected 7 sda/out1 open drain i/o sda/out1 and scl/out2 are dual function pins. when in i 2 c mode (see addr/ orient pin), sda/out1 is the sda data signal and scl/out2 is the scl clock signal of the i 2 c interface. when the device is in gpio mode (see addr/orient pin), these pins are out1 and out2 inputs (i) or outputs (o) are shown below: id pin out1 (i/o) out2 (i/o) functionality high?z high?z (o) low (o) no device attached high?z high?z (o) high?z (o) sink with default current high?z low (o) high?z (o) sink with 1.5 a current high?z low (o) low (o) sink with 3 a current low high (i) high (i) source with default current low low (i) high (i) source with 1.5 a current low low (i) low (i) source with default current low high (i) low (i) reserved (do not use) 8 scl/out2 open drain i/o gpio pin interface 3 port/ debug_n input then push/pull output port/debug_n is a dual function pin: 3 state input to set the port role. on the falling edge of en_n and when vdd is active or during power up when en_n is low, the state of this pin is sampled. this pin is also sampled on a sw_res soft reset via i 2 c. high = FUSB303 as a source only port float = FUSB303 as a dual role port (drp) low = FUSB303 as a sink only port subsequently, this pin is the debug_n push?pull output low = debug accessory detected high = debug accessory not detected 5 addr/ orient input then push/pull output addr/orient is a dual function pin: 3 state input to set to i 2 c mode and the i 2 c address or for gpio mode. on the falling edge of en_n and when vdd is active or during power up when en_n is low, the state of this pin is sampled. this pin is also sampled on a sw_res soft reset via i 2 c. high = i 2 c mode with address 62h float = gpio mode low = i 2 c mode with address 42h subsequently, this pin is the orient push?pull output low = cc is cc1 or a5 of the usb?c receptacle high = cc is cc2 or b5 of the usb?c receptacle 9 id open?drain output open drain output that indicate FUSB303?s detection state as a source or sink low = FUSB303 attached as a source high?z = FUSB303 attached as a sink 11 en_n input active low device enable input (has internal pull up resistor)
FUSB303 www. onsemi.com 6 table 3. orient pin versus orient [1:0] register bits mapping cc1 (a5) cc2 (b5) status. orient[1] bit status. orient[0] bit addr/orient pin output FUSB303 connected as a sink snk. open snk. open 0 0 low snk. open snk. rp 1 0 high snk. rp snk. open 0 1 low snk. rp (note 2) snk. rp 0 1 low snk. rp snk. rp (note 2) 1 0 high FUSB303 connected as source src. open src. open 0 0 low src. open or src. ra src. rd 1 0 high src. rd src. open or src. ra 0 1 low src. rd (note 1) src.rd 0 1 low src. rd src. rd (note 1) 1 0 high 1. orientation decoded on this pin after a sink debug test system (dts) attached to FUSB303. 2. orientation decoded on this pin after a source debug test system (dts) attached to FUSB303. high voltage tolerance on ccx and vbus pins the FUSB303 has additional protection for the type c connector pins where it can tolerate up to 28v on vbus, cc1 and cc2 to protect against any misbehaving type c device connect to the FUSB303. if vbus tolerance is needed higher than 28v, a 900k resistor can be used externally along with a t ransient voltage suppressor (tvs) to achieve almost any higher voltage tolerance dictated by the tvs chosen. dead battery if power is not applied to FUSB303 and it is attached to a source device, then the source would pull up the cc line connected through the cable. the FUSB303 in response will turn on the pull?down that will bring the cc voltage to a range that the source can detect an attached device and turn on vbus. gpio mode, debug and audio accessories when vdd is active and on the trailing edge of en_n, the FUSB303 will sample port/debug_n to determine if the FUSB303 operates as a source (high), sink (low) or drp (floating). subsequently the port/debug_n will be set low when a debug test system is detected. if the FUSB303 is configured as a sink (port/debug_n= low upon enable), the FUSB303 will detect a debug test system if rp is detected on both cc1 and cc2. devices that support orientation detection will also have addr/orient set based on the levels detected for cc1 and cc2. id will be set high?z. if the device is configured as a source (port/debug_n= high upon enable), the FUSB303 will detect a debug test system if rd is detected on both cc1 and cc2. devices that support orientation detection will also have addr/orient set based on the levels detected for cc1 and cc2. id will be set low. the FUSB303 also supports drp toggling for detecting debug test systems. when port/debug_n= float upon enable, the FUSB303 can detect both source and sink debug test systems depending on how it resolves its role as a source or sink. then it acts either as a source or sink as described above. the FUSB303 will report debug test system detection via the type i 2 c register as well. the detection is the same as described above except source, sink and drp roles are configured via the portrole register. this portrole register setting has higher priority over the port/debug_n pin state for source/sink/drp port role. the FUSB303 will set int_n/out3 = low in gpio mode when an audio accessory is detected. the FUSB303 will report audio accessory detection via the type i 2 c register as well when audio accessory detection is configured via the portrole register. force.snk and force.src functionality in some cases, a device may need to force its role to a sink or a source especially if two drp devices are connected together and they have connected in the wrong device role. in that case, the FUSB303 has incorporated a function that allows it to be forced into either sink or source. however, if it cannot complete this role change, the FUSB303 will resume its previous role and flag success or failure with i_frc_succ and i_frc_fail interrupts respectively. remedial actions in some cases, a device may start to detect a source or sink but get caught in a loop trying to resolve the detected device.
FUSB303 www. onsemi.com 7 in that case the FUSB303 provides functionality to resolve to a stable attached state. this functionality can be turned on and off via the remedy_en and dcable_en bits. multiple cases are tried and some of the register settings will be changed to try to achieve stable attach. the i_remedy interrupt will allow the processor to know that this functionality has been triggered. autosnk mode when the FUSB303 is powered directly from vbat the auto_snk_en mode can be used to prevent the application from attaching as a source when the battery is weak or disconnect and attach as a sink. with auto_snk_en enabled the port will attempt to configure as a sink when attached to another drp. if connected to another sink, the port will detach. the threshold at which autosnk can be triggered can be programmed via the auth_snk_th bits. the i_autosnk interrupt is triggered whenever this functionality is invoked. power up, initialization and reset, interrupt operation, i 2 c interface the FUSB303 includes a full i 2 c slave controller. the i 2 c slave fully complies with the i 2 c specification version 6 requirements. this block is designed for fast mode. examples of an i 2 c write and read sequence are shown figure 5 and figure 6 respectively. note: single byte write is initiated by master with p immediately following the first data byte and slave a figure 5. i 2 c write example s slave address wr register address k a a write data a write data k+1 a write data k+2 a write data k+n?1 a p 8bits 8bits 8bits note: if register is not specified master will begin read from current register. in this case only sequence showing in red brack et is needed figure 6. i 2 c write example single or multi byte read executed from current register location (single byte read is initiated by master with na immediately following first data byte s slave address wr a register address k a s slave address rd a read data k a read data k+1 a read data k+n?1na p 8bits 8bits 8bits 8bits register address to read specified s start condition a acknowledge (sda low) na not acknowledge (sda high) wr write=o rd read =1 p stop condition from master to slave from slave to master when power is first applied, the FUSB303 will power up in the configuration set by the por t/debug_n input with audio accessory support enabled and all interrupts masked. if the addr/orient input is high or low (i 2 c mode) the local processor can then re?configure the FUSB303 to the desired mode and clear the global interrupt mask bit, int_mask using the i 2 c interface. the int_n/out3 pin is an active low , open drain output. this pin indicates to the host processor that an interrupt has occurred in the FUSB303 which needs attention. the int_n/out3 pin is in a high impedance state by default after power?up or device reset, and the global interrupt mask (int_mask in control register) is set. after int_mask bit is cleared by the local processor, the int_n/out3 pin stays high impedance in preparation of future interrupts. when an interruptible event occurs, int_n/out3 is driven low and is in a high impedance state again when the processor c lears the interrupt by writing a one in the position of the interrupt bit that was set. subsequent to the initial power up or reset; if the processor writes a ?1? to global interrupt mask bit when the system is already powered up, the int_n/out3 pin stays in a high impedance state and ignores all interrupts until the global interrupt mask bit is cleared. if an event happens that would ordinarily cause an interrupt when the global interrupt mask bit is set, the int_n/out3 pin goes low when the global interrupt mask is cleared. interrupt bits hold their value and to clear a specific interrupt, a ?1? needs to be written to that interrupt bit.
FUSB303 www. onsemi.com 8 i 2 c address the addr/orient bit high or low is indicated in bit 5 of the slave address shown in table 4. table 4. FUSB303 i 2 c slave address name size (bits) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 slave address 8 0 1 addr/orient state 0 0 0 1 r/w table 5. absolute maximum ratings symbol parameter min. max. unit v vdd supply voltage from v dd ?0.5 6.0 v v con id, vbus_det, cc1 and cc2 voltage ?0.5 28.0 v v io port/debug_n, addr/orient, int_n/out3, sda/out1, scl/out2 pins voltage ?0.5 6.0 v v io en_n ?0.5 2.0 v t storage storage temperature range ?65 +150 c t j maximum junction temperature +150 c t l lead temperature (soldering, 10 seconds) +260 c esd iec 61000?4?2 system esd with external tvs connector pins (vbus, cc1 & cc2) air gap 15 kv contact 8 human body model, jedec jesd22?a114 connector pins (vbus_det, cc1 and cc2) 4 kv others 2 charged device model, jedec lesd22?c101 all pins 1 stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. table 6. recommended operating conditions symbol parameter min. typ. max. unit v bus vbus_det voltage 4.0 5.0 22 v v dd supply voltage 2.85 3.3 5.5 v t a operating temperature ?40 +85 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability.
FUSB303 www. onsemi.com 9 table 7. dc and transient characteristics (unless otherwise specified: recommended t a and t j temperature ranges. all typical values are at t a = 25 c and v dd = 3.3 v unless otherwise specified.) symbol parameter t a = ?40 to +85 c t j =?40 to +125 c unit min. typ. max type c specific parameters i 80_ccx source 80 a cc current (default) host_cur1 = 0, host_cur0 = 1 or via gpio mode 64 80 96 a i 180_ccx source 180 a cc current (1.5 a) host_cur1 = 1, host_cur0 = 0 or via gpio mode 166 180 194 a i 330_ccx source 330 a cc current (3 a) host_cur1 = 1, host_cur0 = 1 or via gpio mode (note 3) 304 330 356 a v snkdb sink pull?down voltage in dead battery under all pull?up source loads 2.18 v rd sink pull?down resistance when vdd is within operating range 4.6 5.1 5.6 k zopen cc resistance for disabled state 126 k vra?srcdef ra detection threshold for cc pin for source for default current on vbus (host_cur1/0 = 01) or via gpio mode 0.15 0.20 0.25 v vra?src1.5a ra detection threshold for cc pin for source for 1.5 a current on vbus (host_cur1/0 = 10) or via gpio mode 0.35 0.40 0.45 v vra?src3a ra detection threshold for cc pin for source for 3 a current on vbus (host_cur1/0 = 11) or via gpio mode 0.75 0.80 0.85 v vrd?srcdef rd detection threshold for source for default current (host_cur1/0 = 01) or via gpio mode 1.50 1.60 1.65 v vrd?src1.5a rd detection threshold for source for 1.5 a current (host_cur1/0 = 10) or via gpio mode 1.50 1.60 1.65 v vrd?src3a rd detection threshold for source for 3 a current (host_cur1/0 = 11) or via gpio mode (note 3) 2.45 2.60 2.75 v vra?snk ra detection threshold for cc pin for sink 0.15 0.20 0.25 v vrd?def rd default current detection threshold for sink 0.61 0.66 0.70 v vrd?1.5a rd 1.5 a current detection threshold for sink 1.16 1.23 1.31 v vrd?3.0a rd 3 a current detection threshold for sink 2.04 2.11 2.18 v vvbusthr vbus_det threshold when vbusok is deasserted 2.9 3.3 3.67 v vvbusdeb vbus_det debounce time before vbusok is deasserted only (see tdeb below for vbusok being asserted) 10 20 ms vvbthlh vbus_det threshold when vbusok is asserted 3.67 4.07 4.48 v tdeb vbus_det debounce time before vbusok is asserted 250 500 s vvsafethr vsafe0v vbus_det threshold 0.8 v vvsafethrhys vsafe0v vbus_det threshold hysteresis 50 mv rvbusleak leakage between vbus and gnd when vbus not sourced 72.4 k rvbusdschg effective resistance from vbus and gnd when vbus is being discharged from vsafe5v v dd (v) = 2.85 to 5.5 2 k rpullup pull up resistor to vdd value on en_n pin v dd (v) = 2.85 to 5.5 6 m vautosnkthr weak battery vdd threshold ?3% auto snk_t h +3% v ra resistor for discharging vconn v dd (v) = 2.85 to 5.5 1 k 3. vdd = 3 v when 3 a current advertised.
FUSB303 www. onsemi.com 10 table 8. current consumption symbo l parameter vdd (v) conditions ta = ?40 to +85 c tj=?40 to +125 c unit min. typ. max. idisable disabled current 2.85 to 4.35 disabled state en n = high or not connected 5 a istby unattached sink (3.3 v i 2 c mode without autosnk or accessories) 2.85 to 4.35 nothing attached 5 10 a unattached drp or source (3.3 v i 2 c mode without autosnk or accessories) nothing attached, internally toggling 10 15 a iattach attached source or sink (3.3 v i 2 c mode without autosnk or accessories. not including ixxx_ccx current) 2.85 to 4.35 attached as a sink or source 10 15 a table 9. timing parameters symbol parameter t a = ?40 to +85 c t j =?40 to +125 c unit min. typ. max. unit tccdebounce debounce time for cc attach detection (tccdeb[2:0] = 011) ?33% tccde b +33% ms tpddebounce time a sink port shall wait before it can determine it is detached 10 15 20 ms ttryccdebounce time a port shall wait before it can determine it is re?attached during the try?wait process 10 20 ms trpvaluechange time a sink port shall wait before it can determine there has been a change in rp 10 20 ms tsrcdisconnect time a source shall detect the src.open state 10 20 ms terrorrecovery time staying in the errorrecovery state if sent there via the error_rec bit or by a change of port roles 25 50 100 ms tdrptry time staying in the try.src/snk prior to transition to trywait.src/snk state 75 150 ms ttrytimeout time to discharge vbus before giving up for cases where vbus is always on. 550 1100 ms tdrp sum of tdrptogsnk and tdrptogsrc ?33% t_drp +33% ms tdrptransition time drp shall complete transitions between source and sink roles 0 1 ms tdrptogsnk for drp operation, time spent in unat- tached.snk before going to unattached.src state drptoggle = 00 (note 4) 70 % drptoggle = 01 60 % drptoggle = 10 50 % drptoggle = 11 40 % tdrptogsrc for drp operation, time spent in unat- tached.src before going to unattached.snk state drptoggle = 00 (note 4) 30 % drptoggle = 01 40 % drptoggle = 10 50 % drptoggle = 11 60 % ten time from en_n low and vdd active to i 2 c access available 2.85 to 5.5 100 ms
FUSB303 www. onsemi.com 11 table 9. timing parameters (continued) symbol parameter t a = ?40 to +85 c t j =?40 to +125 c unit min. typ. max. unit treset soft reset duration 2.85 to 5.5 100 ms tautosnk debounce time to detect weak battery vdd threshold to trigger i_autosnk if autosnk mode enabled for both entering autosnk and exiting autosnk v dd ( v) = 2.85 to 5.5 10 15 20 ms 4. default value when configured in gpio mode (addr/orient = float) table 10. io specifications symbol parameter v dd (v) conditions t a = ?40 to +85 c t j =?40 to +125 c uni t min. typ. max. open drain output pins (id, int_n/out3) v olid output low voltage 2.85 to 5.5 i ol = 4 ma 0.4 v input pin (en_n) v ilen low?level input voltage 2.85 to 5.5 0.4 v v ihen high?level input voltage 2.85 to 5.5 1.2 v i ccten vdd current when en_n is high 2.85 to 5.5 worst input voltage 2 a 3?state input and push/pull output pins (port/debug_n, addr/orient) v iladdr low?level input voltage 2.85 to 5.5 0.2v dd v v imaddr middle?level input voltage 2.85 to 5.5 0.4v dd 0.6v dd v v ihaddr high?level input voltage 2.85 to 5.5 0.8v dd v zfloat impedance to vdd or gnd detected as a float including when vdd = 0 2.85 to 5.5 1 4 m v olout low?level input voltage 2.85 to 5.5 i ol = 1 ma 0.2v dd v v ohout high?level input voltage 2.85 to 5.5 i ol = ?1 ma 0.8v dd v i 2 c interface pins ? fast mode sda/out1, scl/out2 v ili2c low?level input voltage 2.85 to 5.5 0.4 v v ihi2c high?level input voltage 2.85 to 5.5 1.2 v v hys hysteresis of schmitt trigger inputs 2.85 to 5.5 0.2 v i i2c input current of sda/out1and scl/out2 pins, 2.85 to 5.5 input voltage 0 v to 3.6 v 2 a i ccti2c vdd current when sda/out1or scl/out2 is high 2.85 to 5.5 worst input voltage 2 a v olsda low?level output voltage at 2 ma sink current (open?drain) 2.85 to 5.5 i ol = 2 ma 0.3 v i olsda low?level output current (open?drain) 3.0 to 5.5 v olsda = 0.4 v 20 ma c i capacitance for each i/o pin 2.85 to 5.5 5 pf
FUSB303 www. onsemi.com 12 table 11. fast mode i 2 c timing specifications (see figure 7) symbol parameter fast mode min. max. unit f scl scl/out2 clock frequency 400 khz t hd;sta hold time (repeated) start condition 0.6 s t low low period of scl/out2 clock 1.3 s t high high period of scl/out2 clock 0.6 s t su;sta set?up time for repeated start condition 0.6 s t hd;dat data hold time 0.9 s t su;dat data set?up time (note 5) 100 ns t r rise time of sda/out1 and scl/out2 signals (note 6) 20 (v dd /5.5 v) 250 ns t f fall time of sda/out1 and scl/out2 signals (note 6) 20 (v dd /5.5 v) 250 ns t su;sto set?up time for stop condition 0.6 s t buf bus?free time between stop and start conditions 1.3 s t sp pulse width of spikes that must be suppressed by the input filter 50 ns 5. a fast?mode i 2 c?bus device can be used in a standard?mode i 2 c?bus system, but the requirement t su;dat 250 ns must be met. this is automatically the case if the device does not stretch the low period of the scl/out2 signal. if such a device does stretch the low period of the scl/out2 signal, it must output the next data bit to the i 2 c_ line tr_max + t su;dat = 1000 + 250 = 1250 ns (according to the standard?mode i 2 c bus specification) before the scl/out2 line is released 6. cb equals the total capacitance of one bus line in pf. if mixed with high?speed devices, faster fall times are allowed accor ding to the i 2 c specification sda scl low hd;sta hd;dat high su;dat su;sta sr hd;sta sp su;sto buf p s t t t t t t tt t t t t t r f r s t f figure 7. definition of timing for full/speed mode devices on the i 2 c bus
FUSB303 www. onsemi.com 13 register definitions table 12. register map address register name type rst val bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h reserved n/a n/a do not use 01h device id r 10h ver_id[3:0] rev_id[3:0] 02h device type r 01h device_type[7:0] 03h portrole r/w 4nh (see below) orientd eb try[1:0] audioac c drp snk src 04h control r/w 4bh t_drp drptoggle[1:0] dcable_ en host_cur[1:0] int_mas k 05h control1 r/w b3h remedy _en auto_snk_th[1:0] auto_sn k_en enable tccdeb[2:0] 06h-08h reserved n/a n/a do not use 09h manual w/c & r/w 00h force_s rc force_s nk unatt_s nk unatt_s rc disable d error_ rec 0ah reset w/c 00h sw_res 0bh-0dh reserved n/a n/a do not use 0eh mask r/w 00h m_orien t m_fault m_vbus_ chg m_auto snk m_bc_lv l m_detac h m_attac h 0fh mask1 r/w 00h m_rem_ vboff m_rem_ vbon m_rem_f ail m_frc_f ail m_frc_s ucc m_reme dy 10h reserved n/a n/a do not use 11h status r 40h autosn k vsafe0v orient[1:0] vbusok bc_lvl[1:0] attach 12h status1 r 00h fault remedy 13h type r 00h debugs rc debugs nk sink source activec able audiovb us audio 14h interrupt r/w1 c 00h i_orient i_fault i_vbus_ chg i_autos nk i_bc_lvl i_detac h i_attach 15h interrupt1 r/w1 c 00h i_rem_v boff i_rem_v bon i_rem_f ail i_frc_fa il i_frc_s ucc i_remed y 16h-1fh reserved n/a n/a do not use 7. do not use registers that are blank 8. values read from undefined register bits are not defined and invalid. do not write to undefined registers table 13. device id (address: 01h, reset value: 0001_0000b, type: read only) bit # name size (bits) description 7:4 ver_id 4 device version id by trim, etc. a_[rev_id]: 0001 (FUSB303 a) 3:0 rev_id 4 revision history of each version [ver_id]_reva: 0000
FUSB303 www. onsemi.com 14 table 14. device type (address: 02h, type: read only) bit # name size (bits) description 7:0 device_type[7:0] 8 01h: FUSB303 02h: FUSB303t (metal option without dead battery rd pull?downs) table 15. portrole (see note 9) (address: 03h, reset value: 0100_1nnnb (reset value for bits nnn will be set by the state of the port/debug_n pin either during power up when en_n is low or when vdd is valid and en_n goes high to low) or when sw_res is set high. in dead battery mode, nnn = 010 or configured as snk) type: read/write) bit # name size (bits) description 7 reserved 1 do not use 6 orientdeb 1 1: when a debug accessory is found, continue to orientation de- tection if cc is on cc1 or cc2 (result is in status.orient[1:0]) 5:4 try[1:0] 2 00: disable (normal drp detection for drps) 01: enable try.snk state machine detection for drp only 10: enable try.src state machine detection for drp only 11: disable (cannot have try.snk and try.src active together) 3 audioacc 1 1: enable audio accessory support (debug accessory support is always enabled) 2 drp 1 1: configure device as a dual role port (see reset value text above) 1 snk 1 1: configure device as a sink (see reset value text above) 0 src 1 1: configure device as a source (see reset value text above) 9. if drp bit, snk bit and src bit are all set to 1, then the priority of which portrole the FUSB303 assumes is first priority i s drp, second priority is snk and last priority is src. see manual register note below for priority between manual register bits and portrole registe r. table 16. control address: 04h, reset value: 0100_1011b, type: read/write bit # name size (bits) description 7:6 t_drp[:0] 2 sets the total period of the drp toggle cycle (i.e. unattached.snk period + unattached.src period): 00: 60 ms 01: 70 ms 10: 80 ms 11: 90 ms 5:4 drptoggle[1:0] 2 selects different timing for dual role port toggle between unattached.snk state and unattached.src state. 00: 60% in unattached.snk and 40% in unattached.src 01: 50% in unattached.snk and 50% in unattached.src 10: 40% in unattached.snk and 60% in unattached.src 11: 30% in unattached.snk and 70% in unattached.src 3 dcable_en 1 1: enable dangling cable internal methods to achieve a stable attach 2:1 host_cur[1:0] 2 controls the pull?up current when device enabled as a source 00: reserved. do not use. 01: 80 a ? default usb power 10: 180 a ? medium current mode: 1.5 a 11: 330 a ? high current mode: 3 a 0 int_mask 1 1: global interrupt mask to mask all interrupts
FUSB303 www. onsemi.com 15 table 17. control1 (address: 05h, reset value: 1011_0011b, type: read/write) bit # name size (bits) description 7 remedy_en 1 1: enable the remedy detection to employ internal methods to achieve stable attach 6:5 auto_snk_th [1:0] 2 sets the weak battery vdd threshold voltage when auto_snk_en is enabled. 00: 3.0 v 01: 3.1 v 10: 3.2 v 11: 3.3 v 4 auto_snk_en 1 1: enable automatic sink port role based on weak battery vdd threshold in bits auto_snk_th in control register below 3 enable 1 1: enable the FUSB303 if the external en_n pin is low in i 2 c mode (that is, not in gpio mode) 2:0 tccdeb[2:0] 3 controls debounce time for attaching a device 000: 120 ms 001: 130 ms 010: 140 ms 011: 150 ms 100: 160 ms 101: 170 ms 110: 180 ms 111: reserved table 18. manual (note 10) (address: 09h, reset value: 0000_0000b, type: read/write (see bits below: w/c = write one self clearing, r/w = read/write and n /a = not applicable) bit # name r/w/c size (bits) description 7:6 reserved n/a 2 do not use 5 force_src w/c 1 1: forces the FUSB303 to behave as a source 4 force_snk w/c 1 1: forces the FUSB303 to behave as a sink 3 unatt_snk w/c 1 1: put device in unattached.snk state as defined in the type c spec 2 unatt_src w/c 1 1: put device in unattached.src state as defined in the type c spec 1 disabled (note 11) r/w 1 1: put device in disabled state as defined in the type c spec 0 error_rec w/c 1 1: put device in errorrecovery state as defined in the type c spec 10. if more than one bit is set to 1b simultaneously then an order of priority will be used. first priority is disabled, second is error_rec, third is force_src, fourth is force_snk, fifth is unatt_src, last is unatt_snk. the highest priority bit will take precedence a nd all other bits will be cleared automatically. 11. the disabled bit must be manually cleared. also disabled bit has a higher priority over portrole register since the disabled bit has to be cleared in order to execute the new portrole register settings. however, all other manual register bits don?t have a lot of meaning if the portrole register is changed and so portrole register setting should have higher priority than all bits except for disabled bit. table 19. reset (address: 0ah, reset value: 0000_0000b, type: write/clear) bit # name size (bits) description 7:1 reserved 7 do not use 0 sw_res 1 1: reset the FUSB303 and i 2 c registers
FUSB303 www. onsemi.com 16 table 20. mask (address: 0eh, reset value: 0000_0000b, type: read/write) bit # name size (bits) description 7 reserved 1 do not use 6 m_orient 1 1: mask the i_orient interrupt bit from asserting int_n pin 5 m_fault 1 1: mask the i_fault interrupt bit from asserting int_n pin 4 m_vbus_chg 1 1: mask the i_vbus interrupt bit from asserting int_n pin 3 m_autosnk 1 1: mask the i_autosnk interrupt bit from asserting int_n pin 2 m_bc_lvl 1 1: mask the i_bc_lvl interrupt bit from asserting int_n pin 1 m_detach 1 1: mask the i_detach interrupt bit from asserting int_n pin 0 m_attach 1 1: mask the i_attach interrupt bit from asserting int_n pin 12. masking the interrupt just does not cause int_n to be asserted. the interrupt bit will still be asserted in the interrrupt register and so that an all zeroes interrupt register value is not needed for int_n to be deasserted. table 21. mask1 (address: 0fh, reset value: 0000_0000b, type: read/write) bit # name size (bits) description 7 reserved 1 do not use 6 m_rem_vboff 1 1: mask the i_rem_vboff interrupt bit from asserting int_n pin 5 m_rem_vbon 1 1: mask the i_rem_vbon interrupt bit from asserting int_n pin 4 reserved 1 do not use 3 m_rem_fail 1 1: mask the i_rem_fail interrupt bit from asserting int_n pin 2 m_frc_fail 1 1: mask the i_frc_fail interrupt bit from asserting int_n pin 1 m_frc_succ 1 1: mask the i_frc_succ interrupt bit from asserting int_n pin 0 m_remedy 1 1: mask the i_remedy interrupt bit from asserting int_n pin 13. masking the interrupt just does not cause int_n to be asserted. the interrupt bit will still be asserted in the interrrupt r egister and so that an all zeroes interrupt register value is not needed for int_n to be deasserted table 22. status (address: 11h, reset value: 0000_0000b, type: read only) bit # name size (bits) description 7 autosnk 1 1:autosnk mode is activated since the vdd voltage is lower than au- to_snk_th voltage 6 vsafe0v 1 1: status to indicate vbus_det is below vsafe0v max of 0.8 vpin 5:4 orient[1:0] 2 status to indicate which ccx pins has the cable cc connection 00: no or unresolved connection detected 01: cable cc is connected through the cc1 (a5) pin 10: cable cc is connected through the cc2 (b5) pin 11: a fault has occurred during the detection 3 vbusok 1 1: status to indicate vbus_det is in the valid vbus 5v range 2:1 bc_lvl[1:0] 2 thresholds that allow detection of current advertisement on cc line 00: (ra or unattached) sink or unattached source 01: rd threshold for sink default current advertisement 10: rd threshold for sink 1.5 a current advertisement 11: rd threshold for sink 3 a current advertisement 0 attach 1 1: attached to a device or accessory of a type shown in the type register
FUSB303 www. onsemi.com 17 table 23. status1 (address: 12h, reset value: 0000_0000b, type: read only) bit # name size (bits) description 7:2 reserved 6 do not use 1 fault 1 1: status to indicate that as a sink, cc has exceed the normal vrd voltage range 0 remedy 1 1: status to indicate that FUSB303 is employing internal methods to achieve a stable attach table 24. type (address: 13h, reset value: 0000_0000b, type: read only) bit # name size (bits) description 7 reserved 1 do not use 6 debugsrc 1 1: FUSB303 is attached as a source debug accessory ([unoriented/oriented]debugaccessory.src) 5 debugsnk 1 1: FUSB303 is attached as a sink debug accessory (debugaccessory.snk) 4 sink 1 1: FUSB303 is attached as a sink (attached.snk) 3 source 1 1: FUSB303 is attached as a source (attached.src) 2 activecable 1 1: FUSB303 is attached to an active cable (ra detected) 1 audiovbus 1 1: indicates an audio accessory with vbus has been detected (audioaccessory with vbus) 0 audio 1 1: indicates an audio accessory without vbus has been detected (audioaccessory without vbus) table 25. interrupt (address: 14h, reset value: 0000_0000b, type: read/write 1 to clear) bit # name size (bits) description 7 reserved 1 do not use 6 i_orient 1 1: interrupt flagged whenever orient changes from 0,0 to 0,1 or 1,0 but not 1,1. interrupt not flagged when orient is cleared. 5 i_fault 1 1: interrupt flagged when cc1 or cc2 voltage exceeds normal rd range when FUSB303 has rd termination on cc1 and/or cc2 4 i_vbus_chg 1 1: interrupt flagged when vbus has crossed vvbusthr or vvbthlh thresh- olds 3 i_autosnk 1 1: interrupt flagged when autosnk mode has been activated or deactivat- ed 2 i_bc_lvl 1 1: interrupt flagged when a change in bc_lvl[1:0] advertised current level has occurred 1 i_detach 1 1: interrupt flagged when a device or accessory has been detached 0 i_attach 1 1: interrupt flagged when a device or accessory of type indicated in the type register has been attached
FUSB303 www. onsemi.com 18 table 26. interrupt1 (address: 15h, reset value: 0000_0000b, type: read/write 1 to clear) bit # name size (bits) description 7 reserved 1 do not use 6 i_rem_vboff 1 1: interrupt to request vbus be turned off and discharged while executing internal methods to achieve stable attach 5 i_rem_vbon 1 1: interrupt to request vbus be turned on while executing internal methods to achieve stable attach 4 reserved 1 do not use 3 i_rem_fail 1 1: interrupt to indicate that internal methods to achieve stable attach have failed. 2 i_frc_fail 1 1: interrupt to indicate that force_src or force_snk has failed to exe- cute either because it was being forced into a state it was already in or for other reasons 1 i_frc_succ 1 1: interrupt to indicate that force_src or force_snk has successfully being executed. 0 i_remedy 1 1: interrupt to indicate that detection issues caused FUSB303 to employ internal methods to achieve stable attach
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